How is setup time calculated

Nice work: I have a doubt in question1: Suppose there are setup and hold times for FF1,the should we include them in the calculation of Tclk..? If yes,please help me with the calculation. If no,whats the reason? If you are talking about the FF1 - and that's the launch FF, then first of all - that will not be the path of Tclk. That will be the part of Td data path delay.

Second thing - for setup and hold violation we calculate at the Capture FF.. I hope.. Hi Sir, I gone through your "Set up and Hold time" part of the blog.

I'm still confused sir, My doubts are: 1 In first question, when finding the hold time violation you have calculated tclk including the hold time in it and then subtracted the tclk from td. My doubt is can I calculate tclk without including the thold and subtract the tclk from td and say that hold time violation occurs when the difference is not greater than 2 t hold..? My doubt is why you didnt consider the tC2q delay in the above calculation.

Also while finding the tclk min delay you have only considered 2ns from U8 ignoring the delays due to flipflop U2. Why was that done..? Sir, please reply ASAP,have an interview scheduled in few days. Clarity in these things will be really helpful.

I have explanied the same thing in my latest blog also.. Please refer that for the details When you are calculating the Clock path delay -- then you consider the Tck2q delay of the launch FF. Not of the capture FF. In the above case - U1 is the capture FF. So we will not consider the Tck2q delay of that in our calculation. I hope this point is clear. In the last I will say only one thing - Dnt try to remember the formulas - just remember the concepts- then you can automatically come to know where to use Tck2q and Tsetup and Thold.

Still in case you have any doubt - Please drop me a mail. I will try my best. And my second question is that in calculating clock path delay for hold analysis we added hold time but for setup time analyses we are subtracting the setup time in clock path delay.. Please reply ASAP. Hi Divya, I will suggest to read the other comment also.

Some time it will help you to remove all your confusion. The Reason we are subtracting the setup value because as per the setup defination.. Same explanation for hold analysis. I will appreciate if you can answer one query. I have the same doubt too. Since the skew is 0 U2 goes to the launch and capture flop. So we consider only that path which has the max delay. You said we need to take max path for clock to out path in Problem 2.

Similar question but with respect to input to reg path was asked in the post.. I have replied similar type of question in the previous part.. Its similar to problem no 1. Just where you have to calculate the max.. Firstly, Pretty good blog : I have a doubt with respect to problem 2: Setup Time calculation: If I have understood correctly, then Datapath is a path which has start point as either input port or clock pin of FF and has end point as data input pin of FF or output port of design.

In this question no 2. Why are these paths are not datapath? You have considered only 2 data paths. Similarly others. Thanks Vikram. Hi Vikram, I have mentioned in my few previous comments also. I would say you try with them and let me know in case any difference are there in the results. Consider this an exercise for you. Why have you not considered c2q delay of u8 ff, delay of AND gate , and clock delay of u9 flip flop. What the exact path??

Can you do the calculation and let me know. I will check on my end and if its looks to me that it's perfect I will change my calculation. First of all thanks sir for the wonderful post on timing analysis, it is indeed very lucid. Sir i have a doubt in ques 2.

Sir correct me if i am wrong but setup and hold are calculated for sequential circuit so what does it mean to calculate at the input?? Sir can you please explain why is setup time off flip flop added when computing the register to register delay in problem 2. Hello Sir, If there is a hold violation found after a design has been taped out, will the chip work properly? Or is there any remedy for this situation? If you read carefully then you come to know that in part a - we are talking about "How to calculate the setup Time" but above we are talking about the "Setup slack" which help to calculate the Setup violation.

Try once again to read both with this view, if still you think there is any confusion - Please reply me back. As I have mentioned that there 2 things are different. In one case, we are talking about how Setup time is calculated and then this Setup time become part of Flipflop Specification. In second case, we are talking about - setup Slack. Means Setup time of Flipflop is fixed which came from the first Case , now we are trying to calculate if given circuit meets the Setup requirement of Flipflop or not.

Please let me know if above description helps you. If still Any confusion - please help me to understand where is the confusion. The contents are good but the grammar could be made better for an user to get a clear understanding of the concepts.

Also the contents have to better organized to avoid confusions. I got confused in problem 1 on where clock period of 15ns is defined. The "Note" section that is put above clock delay calculation section should ideally be put after the calculation as it is misleading, that user will take to be the "Note" section for the previous data path delay calculation.

Awesome blog for timing related concepts. Explained in the best possible manner. Am I correct? Also, going with this method, in the 3rd problem, if we put a 2ns buffer just before clk pin of U9 and a 0. Please clarify. For calculating maximum frequency, we need to consider input to register path too right?? Hi, can you Please elaborate why setup time of FF2 is subtracting in last problem for setup analysis and holding is adding.

Hi, I have one doubt in 2nd question for finding Maximum Frequency. In your earlier post you have mentioned that there are 4 timing paths: 1. My doubt is that why have you considered clock to output path.

Shouldn't it be Register clock pin of FF to output path?? Why it also needs to meet clk to output path and pin to pin path in the 2nd problem? Such horrid English. Besides in 1st sum you are contradicting to what you mentioned in previous blogs. As per the 1st example you have done it the other way round.

I am a newbie to these concepts and confusing people like me is just not right. Hi, First of all, amazing work.

Hats off to you! I just have a single doubt. Shouldn't the Clk2out path start from a clock source and end at the output pin? I read some articles on this site and I think your blog is really interesting and has great information. Thank you for your sharing. Great blog. Just one doubt In ques 3 why is the max clk to out path not taken?? You have considered the path with min delay. Why Hold time is frequency independent and setup time is frequency dependent?

Sir, I have confusion on the calculation of Clk-to-Out delay of Question 3. Why the maximum clk-to-out path is not taken? Can't we consider the Tc2q delay of two DFF's in a single clk path? I mean is clk path always considered through one DFF only?

Yes, the article I was looking for. Your article gives me another approach on the subject. I hope to read more articles from you. How the setup and hold time equations will be at pre-cts and post-cts stages? Just one question - In the second example, we had calculated the required hold time at A.

It came out to be negative. Is this a violation? My understanding is that there is no requirement of "holding" the signal for some time and that the signal can switch as it already is. If this is correct, why is there a need to improve the timing of the circuit, as in example 3.

Please correct where I am wrong. What is effect of IR drop on the setup and hold time? What is the relation between the rise, fall time and setup, hold time? Can you please show the waveform for the given explanation of the hold violation and setup violation for the given example, with explanation?

It would be great help if you do so, I could not relate the calculations to the results. Hi, very nice post. However I am not able to understand one thing.

In post 3c, it is completely opposite. Can you explain this? Great work sir! I had only one doubt: In step 4 of problem 3 while calculating the clock to output time why did we ignore Tc2q of U1 or Tpd of U5?

As we have to find the maximum clock to output time, don't we have to consider all the paths from clock to output. I know I am going wrong somewhere in my thinking but can't figure out where. Please help Sir! Hi sir, Let's consider in first problem if we have one common buffer for both launch and capture paths.. Hello sir, your post is really helpful for understanding things the right way. I have one doubt.

In setup time violation clock period is added to calculate Tpd clk min. I understood that, But why is not necessary to add the clock period to Tpd clk min while calculating the setup time of an Input? Please clarify on this. Thanks in advance. There are some questions about question number two. First, what is the significance of obtaining the maximum period of the clock? That circuit works as a matter of course when the clock cycle is slow.

Slowing down the cycle is not a problem at all. Shouldn't we get a minimum period? Second, delays in U8 are not considered at all. Because it applies equally to both flip flops.

Third, there is a delay for each unit, and if the input signal does not change during the process of each unit's output signal, each unit will normally produce the output result. Thus, by my calculation, the maximum delay time of step4 is 9 ns of U5. As you have written: When a hold check is performed, we have to consider two things- Minimum Delay along the data path.

Maximum Delay along the clock path. Why is that? You haven't given any explanation about this. Hi sir, I really appreciate the effort put in here. Post are really helpful.

I need one clarity on setup time and hold time equation that you posted in this problem and 2 pages previous to it where you defined setup and hold with respect to Td and Tclk. This is causing contradictions. Can you clarify me on this please. Static Timing analysis is divided into several parts:.

Till now we have discussed a lot of theory about setup and hold time with and without Example. Nobody calculate setup in such way during characterization of std. Okay, as you are saying, lets say that the data is moving close to clock, and at 1ns before the clock edge, the output goes in meta-stability. This 1ns is the setup time. Correct me if I am wrong Now my question is, how that 1ns margin is set to the flipflop?

Is that decided at the time of flipflop design? Please provide the steps. Thanks in advance. This method is obsoleted now. These values stored in the timing model for example in synopsys. If flip-flop has bigger values, than you should design the new flipflop.

Is there any another method for this? I mean in digital way. Suppose for example, I want to design a flipflop using NAND gates, how should I design that flipflop with setup 1ns and hold 0. Expecting the answer in digital electronics perspective. I think everyone is reading into the OPs question incorrectly, which is why the keep asking the same question over and over.

The OP I believe wants to know how one would design the library component of a say a DFF that has a specific setup and hold time. This is the transistor level model the analog circuit that DFFs are comprised of in a standard cell library.

Everyone is too fixated on the 1ns setup, 0. Say you want your DFF to have this characteristic 25ps setup, 0ps hold as opposed to this one 22ps setup, 3ps hold or this one I'm specifically thinking of something like FPGAs, where the vendors regularly work to make all their FFs behave like Xns setup and 0ns hold.

I'm sure that the X value is a target given to the technology node library designers to make their FFs work as fast as possible, or perhaps it's more of a here is a new process node, now just make the FFs as fast as possible, and if someone comes up with a better solution then their FFs have better performance. But hey, what do I know, I'm just guessing as to the whys. What constitutes setup time is a question for the FF designer. On one hand the simplest form is, whatever makes the FF give the right functional answer, at some later time.

But for a synthesis based approach without detailed parasitics and path race checking, another constraint is that setup time makes the FF give the right answer -by the time of its timing model-.

Because close-in, setup time begins to modulate FF delay right before it goes metastable and then fails to catch at all. Depending on which you're more in love with setup or delay time you can come up with different design and design-spec choices.

But it needs to be self- consistent to support synthesis and timing closure. You don't want much hold time certainly, no more than minimum FF delay because data -is- going to change after clock sometimes. While the former check is a circuit driven requirement and can be measured by the same method as in the case of positive edge triggered flip-flops, the later check is rather a design driven check used to model time burrowing and is effectively a virtual setup check.

Figure 4: Setup and hold timing for a positive edge triggered flop and negative level triggered latch. The reason for this check is that unlike a flop, the latch output is not a fixed value during a static clock level.

For example, when clock is low, the flop output remains a constant value from the previously captured data, while in case of a negative latch; the output is same as the input data at that instance. Hence, we have a burrow margin which can be given to data path connected at the output of latch, provided we have ensured correct setup timing with the same setup time as at the closing window near the opening edge as shown in figure 3. Hence, to characterize a negative level triggered latch, the characterization methodology is the same as than in case of a positive edge triggered flop and a similar scenario exists for negative edge triggered flop and positive level triggered latch.

This paper elucidates the methodologies followed for setup analysis; hold analysis and setup dependent hold and hold dependent setup analysis. Discussing on the areas of C-Q delays it traverses from setup time to min pulse width checks too for sequential elements flops and latches. This will help persons across industry to understand the sequential cell timing characterization using SPICE and learnt how to use them to get the correct delay estimation.

No portion of this site may be copied, retransmitted, reposted, duplicated or otherwise used without the express written permission of Design And Reuse. Design And Reuse. Introduction With prior knowledge of delay characterization for combinational standard cells, where the delay values are dependent on the input slew and the output load, one needs to take in account of the propagation delay in picture.

Timing Parameters in a Sequential Cell While the timing parameters of a combinational cell are limited to min and max delays using the input transition, the output load and the timing model of the cell as a set of variables, sequential cells come up with their own set of complex timing checks. Some of the key parameters that we will discuss in this paper include: Setup Time Hold Time Clock to Out C-Q Delay Min Pulse Width Methodology for Finding the Sequential Delays of a Standard Cell With combinational element concerned only with the propagation delay of the cell, the sequential element are bit more complex in this scenario.

This can be easily found out by using spice simulation using below steps: Setup time for Flip Flop: Take a clock of pulse width 10ns i. Keep on bringing the data closer to the active edge of the clock. Note the difference of transition time between data input and the clock active edge.

This will become the setup time of the flop. Figure 1: Setup timing measurement for a positive edge triggered flip-flop. This can be found out by using spice simulations and following the below mentioned steps: Hold Time for Flip Flop: Take a clock of pulse width 10ns i.

Figure 2: Hold timing measurement for a positive edge triggered flip-flop. Figure 3: Min Pulse Width and its relationship with setup and hold time.